1. Field of the Invention
The present invention generally relates to a data processing system wherein the processor initiates parallel access to a level 2 (L2) cache and main memory. More specifically, parallel access is initiated and if the instructions or data are found in the L2 cache, the memory access is aborted before the memory is accessed. Additionally, a novel non-hierarchical memory scheme is disclosed for processor load operations wherein two unique data ports are provided to the processor.
2. Description of Related Art
Many modern computer architectures use a hierarchy of storage elements for fast access to data and instructions. Typically a level 1 (L1) cache is integrated into the central processing unit (CPU) and provides a small (8 kilobytes to 256 kilobytes) fast access storage which can run simultaneously with the CPU. A level 2 cache provides a larger cache with more storage and is located between the L1 cache and the level 3 (L3) main memory (external to the CPU). The L2 cache normally runs at the same speed as the CPU clock and is made up of static random access memory (SRAM). The main memory is several cycles behind the CPU clock speed, due to the slower dynamic random access memory (DRAM) which is used, address translation, arbitration and the like.
Conventional three level memory hierarchy systems have a cache control unit for the L2 cache and a separate storage control unit for main memory. Cache misses occur when the data or instructions that the CPU needs are not in the cache. Normally, L1 cache misses are sent to the L2 cache control unit, which then checks the L2 cache for a hit (desired data or instruction is in the L2 cache). If a L2 miss occurs the request is then sent to the storage control unit to fetch the data from main memory. These events occur sequentially and may cause a substantial amount of idle time for the CPU. That is, a time penalty occurs due to the amount of time needed for the data request to go to the L2 cache, and if a miss occurs to then check the main memory for the data.
In order to minimize the amount of CPU idle time, U.S. Pat. No. 4,663,440 shows a hierarchical memory system wherein a low level memory includes a dual port access to the memory chip(s). A high level memory is also included which interacts serially with one port of the low level memory. This enables serial access of the low level memory by the high level memory to occur in parallel with access of the low level memory by a computer system. However, this system does not disclose concurrent access of different levels of memory when a data miss occurs. European Patent Application 0 468 786 A2 describes a memory system with a separate cache controller and memory controller. A microprocessor initiates a search for data in both the cache and main memory simultaneously. If the data is not found in the cache, then the data can be retrieved from main memory without the penalty of cache lookup latency. However, if the data is found in the cache, then the data need not be retrieved from memory and the access to the memory controller is cancelled. The memory controller then terminates the previously initiated search in main memory by asserting a "hit" line, or deasserting a "miss" line. Either of these actions by the memory controller would communicate the need to terminate the main memory access cycle because the data was found in the cache. Thus, it can be seen that this existing system begins accessing the main memory by arbitrating for the bus, translating memory addresses, searching memory locations which all use memory cycles, i.e. the memory is incapable of being used during the period when these activities are occurring. Therefore, each time the microprocessor searches the cache and memory simultaneously, the memory is accessed and becomes incapable of being used in any other process, such as a direct memory access transfer (DMA) from a peripheral controller, or the like, even when the data is found in the cache. This causes the problem of tying up the memory even when the data is found in the cache.
U.S. Pat. No. 3,896,419 shows a typical processor with an L1 cache and memory. This system checks the cache for the data while a memory retrieval operation is being processed. If the data is found in the cache, the retrieval from memory is blocked. However, a port cycle for retrieving data from the memory must be cancelled when data is found in the cache. Thus, memory operations are impacted even when the data is found in the cache.
IBM Technical Disclosure Bulletin, vol. 26, No. 10B, March 1984, pages 5488-5490 discusses at page 5489 a conventional hierarchical memory system wherein an L2 hit indicates data present in the cache and the desired data is then provided to the L1 cache and the output register
A typical prior art hierarchical memory system is shown in FIG. 1 wherein a CPU 100 includes a L1 cache 102 and is connected to a stand-alone L2 cache controller 106, via data bus 104. L2 cache controller provides address and control information to L2 cache 108 and data is received from the L2 cache along bus 107. Data bus 110 interconnects L2 cache controller 106 with memory controller 112 which provides address and control information to memory 114. The memory address and control information and data received from memory 114 are transferred to memory controller 112 along bus 113. From viewing the memory system architecture of Figure, it can be seen that for a L2 cache hit, the data must be provided from L2 cache 108 to L2 cache controller 106 and then to CPU 100, i.e. two chip crossings. Thus, this conventional system requires additional clock cycles to move the data from the L2 cache through cache controller 106 and onto data bus 104. Similarly, when a cache miss occurs and the data must be retrieved from memory 114, the data must be moved through memory controller 112 and onto data bus 110, and the data must then be moved through the L2 cache controller before being placed on data bus 104 for use by CPU 100 (i.e. three chip crossings).
Therefore, those skilled in the art will understand how a memory system wherein access to the L2 cache and main memory are simultaneously initiated, but which does not cause the main memory to be accessed when the data is found in the L2 cache, is highly desirable. Further, it can be seen that a memory system wherein unique ports are provided that allow a L2 cache to provide data directly to a processing unit, instead of passing it through a cache controller to a L1 cache, will increase the speed and efficiency of the system. Additionally, a unique port that allows a main memory to be directly connected to a L1 cache in the CPU, rather through a memory controller and cache controller, will also increase system efficiency.